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TPLD2001-RJY-EVM: Incorrect watchdog timings

Clément Letonnelier
Expert 2816 points
Part Number: TPLD2001-RJY-EVM

Tool/software:

Hello,

I encountered an odd behavior while using the watchdog time in a design through test on the EVM.

I had set the following:

  • Clock select: OSC0/64
  • Timeout period: 20
  • Output assertion time: 10

I was expecting the watchdog fault to trigger 10ms after the refresh input stop to be toggled.

However, during our tests, the watchdog fault got triggered 15ms after the refresh input stop to be toggled.

It seems the fault is triggered after a delay equal to timeout period + output assertion time.

It's not a big issue for us, we changed the output assertion time as 1 cycle was fine enough but the behavior is either a bug or the description in the datasheet and ICS software has to be modified.

Best regards,

Clément

  • 0
    TI__Intellectual 1490 points

    Hi Clément,

    I've attempted to recreate the scenario you've mentioned, and I haven't encountered the same behavior.

    Here is my setup:

    And my result, tested on TPLD2001-RJY-EVM:

    These results are within expectations.

    To calculate what I should expect, I have calculated the amount of time it takes for watchdog fault to trigger using (Timeout Period) / (OSC0/64) = 20 / (2000 / 64) = 0.640 seconds.

    The watchdog assertion period should be (Output Assertion Time) / (OSC0/64) = 10 / (2000/64) = 0.320 seconds. My results show 316 ms which is acceptable.

    My guess is that you may have a pre-divider on your oscillator (screenshot shown below). Depending on the numbers in your Timeout Period and Output Assertion Time, it might appear that they're being added together when it's actually a pre-divider causing the problem. Or perhaps you're using the watchdog EN input in a way that causes this behavior.  It's hard to determine the cause without seeing your .syscfg file.

    However, it sounds like you've found a way to make your TPLD work the way you want, so I'm glad! If you have any more questions or concerns, please do not hesitate to ask. I appreciate you letting us know when you find potential errors. It's very helpful as we continue to develop InterConnect Studio. We update it regularly with bug fixes and added features.

    Regards,

    Nikki

  • 0 in reply to Nikki Dengel
    Expert 2816 points

    Hello,

    Hum it's honestly strange, I checked my configuration and I don't have a pre-divider.

    If you want to check our syscfg, maybe you can get it as I sent our design through the tool for samples programming.

    I am in contact with Crane Russell for that.

    In any case he also has the syscfg, I sent it to him per email.

    Regards,

    Clément