Help with PCA9515A and I2C bus

Nuba said:

I am trying to build a network between several msp430. My idea was to connect every msp430 to a 5V I2C bus. My MSP430 work at 3.3v so I use a PCA9515A between each msp430 and the bus that does the voltage translation.

But now I am facing this problem: for some reason, after the slave sends the addres ack bit to the master, the signal at the 3.3v slave side is diferent than the signal at the 5v side of the bus. While the signal at the 5v bus side is correct, i have unexpected high levels at the 3.3v slave side.

My guess is that you are running into the issue of the PCA9515A not supporting 2 of these devices in series.  This is indicated on page 2 of the PCA9515A datasheet in the second paragraph.

Yes, I was thinking that.

But what I actually have is not a pure series connection between 2 nodes. I have 4 nodes ina a bus topology. Is that considered series connection for PCA9515?

Perhaps I may not understand your topology.  I have included a picture of what I thought you were describing in your original post.

If this is the case, then the path from one MSP430 to another would go through 2 PCA9515A devices in series with each other.

I would propose a topology as below.

Yes, I have the topology you painted in picture 1. So, is that ever going to work? I have changed the pull up values and now I have the "master transmitting mode" working but not the "master receiving".

Is it anything I can do to make this work or do I have to change my hardware design?

Thanks,

Nuba.

I would like to add that the reazon why the "master receiving" doesn not work seems to be because there are 2 clock pulses missing after  the READ bit sent by the master.

Is this also caused by the series connection of 2 PCA or there is another reazon for this?

Thanks a lot,

Nuba

Are you able to probe with an oscilloscope at all segments of the circuit?

Are you able to determine where the pulses are getting suppressed?

Yes I am able to probe with an osc in all segments.

In the slave transmitting mode there are 2 clk pulses missing at the 5V segment, after the master sends the READ bit. I can see those pulses at the 3.3v segment of the master.

So when the master sends the READ bit in the first byte sent, which includes the SLAvE device address and read/write command bit, the next bit is the ACK/NACK bit.  Is it this bit which you do not see a clock rising edge in the 5V segment?

It would also be interesting to know what the slave side 3.3V segment looks like during this time as well.