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SN74HC163: Parallel Carry N-Bit Counter using SN74HC163

Tatsuki Kamijo
Prodigy 10 points
Part Number: SN74HC163
Other Parts Discussed in Thread: TINA-TI

Hi,
I'm trying to create a Parallel Carry N-Bit Counter using the SN74HC163.
I've confirmed that both the circuit and simulation work without any problems up to 8 bits.
However, when I increase it to 12 bits, both the circuit and simulation behave abnormally.
What is the cause of this abnormal behavior?
The prototype circuit is the same as Figure 2 on the datasheet.
I've attached a simulation image from TINA-TI, so I'd like to first confirm that it works without any problems in simulation.
Thank you in advance.

  • 0
    TI__Intellectual 2330 points

    Hi Tatsuki Kamijo,

    Could you describe the abnormal behavior you're observing? What clock frequency are you using?

    Regards,

    Nikki

  • 0 in reply to Nikki Dengel
    Prodigy 10 points

    Hi Nikki Dengel,

    Since all data inputs in the simulation circuit diagram are set to HIGH, I think 1RCO/2RCO/3RCO should be HIGH and LD should always be LOW.
    However, the simulation results show that 1RCO is HIGH and LOW, and 2RC and 3RCO are LOW. As a result, LD is always outputting HIGH.
    The clock frequency is set to 1kHz in the simulation.
    Therefore, the pulse interval of the LD output is thought to be
    1/X [ms], since 1kHz/(2^12-SetData) = X.
    Regards

  • 0 in reply to Tatsuki Kamijo
    TI__Intellectual 2330 points

    Hi Tatsuki Kamijo,

    Your circuit is correct for an Parallel Carry N-Bit Counter, but I think your initial conditions are incorrect. At the beginning of this simulation, you will not load your inputs to A, B, C, D until the end of the count, at which point A, B, C, D will be loaded into the counters. To load data into the counters, LOAD needs to be low. So in your simulation, LD will be high until 4096 clock cycles before it is low for one cycle. When it is low, ABCD will load into the counters.

    Regards,

    Nikki