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SN74LVC2G126: Ioff feature understanding

Vishnu Jayaraj
Intellectual 295 points

Part Number: SN74LVC2G126

Hi,

Our design has 3V3_A and 3V3_B voltage rails.

3V3_A is main board power and 3V3_B is auxiliary board power but both are generated in main board.

Auxiliary board is plugged to main board (Not hot plug).

These both boards are communicating via UART.

Buffer is located in auxiliary board.

Main board MCU in 3V3_A and auxiliary board MCU in 3V3_B. 

Auxiliary board 3V3_B can be turned off from main board while 3V3_A stays 'ON'

Consider a first time power 'ON' so only 3V3_A generated initially.

There the Ioff feature is applicable since the buffer VCC (3V3_B) is 0V since 3V3_B is still disabled.

Consider 3V3_B is enabled and both board starts communication.

Now if 3V3_B is disabled, the auxiliary board has 100uF bulk capacitor and 3V3_B takes around 10s to drop below 100uV. How  would the Ioff feature behave in this situation? 

As per DS, Ioff feature is mentioned at VCC=0V.

What if buffer VCC is slowly reaching to 0V (>10s) would the Ioff feature work?

Regards

Vishnu

 

  • 0
    Guru 325520 points

    Inputs always are overvoltage tolerant.
    Outputs are overvoltage tolerant when the output is disabled (OE low) or when the device is powered off (VCC near 0 V). (This matters only when another voltage is applied to the output, e.g., with a pull-up resistor.)

  • 0
    Intellectual 295 points

    Hi,

    In our design when buffer is turned off, both input and output lines are pulled to 3V3_A. 

    Our query is when VCC is falling to 0V (takes around 10s) whether leakage will start from input and output pulled up to 3V3_A to 3V3_B supply?

    Is there any detailed explanation/ application note on how Ioff feature work?

    In one of our design we used 'SN74LVC2G17DCKR'. With this part we were seeing leakage voltage from 3V3_A to 3V3_B through buffer, when buffer VCC was taking ~10s to decay to 0V. Ioff feature was not working since buffer VCC were dropping to 0V and leakage already started.

    Could you please share the internal structure details of both SN74LVC2G17DCKR and SN74LVC2G126 ?

    Regards

    Vishnu

  • 0 in reply to Vishnu Jayaraj
    Guru 325520 points

    When the voltage is above zero, and the output is enabled and driving high, then the output is directly connected to VCC, and a current can flow backwards into the output and keep VCC high. To prevent this, disable the output (OE low) before removing VCC.

  • 0 in reply to Clemens Ladisch
    Intellectual 295 points

    "When the voltage is above zero"  Means Buffer VCC?

  • 0 in reply to Vishnu Jayaraj
    TI__Genius 15501 points
    Vishnu Jayaraj said:
    "When the voltage is above zero"  Means Buffer VCC?

    Yes when the VCC of the device is above 0V.

    -Owen