SN74HC165: SN74HC165 data misalignment issue

Haoqi Zheng

Part Number: SN74HC165

Hi there,

I have a design with 8 pcs SN74HC165 in series to get 48 IOs' state (6 IOs for each IC). Each cable is about 500mm in the chassis. Most of the time they works well, but one of the chips had an issue. When data passed through it and was output, it would shift incorrectly. The normal data should be 00111111, but after passing through it, it became 01111110. The problem was resolved after I replaced the chip. Now, our customer wants to know why this happened.

11 months ago

0 Clemens Ladisch 11 months ago

Guru 327970 points

Please zoom in on a rising edge of the CLK signal so that the slope of the clock edge and the state of the data input are visible.

0 Haoqi Zheng 11 months ago

Prodigy 20 points

Sorry, since the chip has been removed, the original waveform cannot be reproduced—only this waveform was saved. Are you suspecting that there might be a timing misalignment between the clock's rising edge and the data transition edge? What specific reasons could lead to such a result? Is it related to the number of chips or the length of the cables?

0 Clemens Ladisch 11 months ago in reply to Haoqi Zheng

Guru 327970 points

I suspect that the clock edge is too slow and exceeds the Δt/Δv limit.

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SN74HC165: SN74HC165 data misalignment issue