SN74AHC595: timing requirements of the SN74AHC595

Part Number: SN74AHC595


Hi expert,

My customers have a questions regarding the timing requirements definition of the SN74AHC595. Does the device read the data on the rising edge of the CLK signal, so that the data/SER signal should be set up at least Tsu before the CLK rising up to 50% and hold on at least Th for remaining the status? Am I understand these timing parameters correctly?

What would happen if the CLK is rising upto 50% before the SER is set up (like waveforms below, blue: SER data, green: SCLK)?

image.png

image.png

BR,

Manu

 

  • Hi Manu,

    Yes, your understanding is correct.

    If the CLK rising edge happens before the data is established for Tsu, incorrect data might be clocked in, or the shift register DFF might enter a metastable state where its output carries an unknown voltage for an unknown period of time, before it settles either high or low unpredictably.

    Best,

    Malcolm