TPLD1201: IO7 output 1.15V during startup

Hello Malcolm,

Yes, 10k PU is external of TPLD1201, to connect IO7 with VCC of TPLD. Here's a test environment:

I was expecting that IO7 will be 3.3V because IO7 is high impedance during startup time. But the oscilloscope CH2 showed 1.15V. Please refer the previous screenshot.

Could you explain the result for me?

Best regards,

Yasunori Okutsu

Hi Yasunori,

A few requests:

1. Could you see what happens if you connect the input of pin IO7 to a couple of different things, such as VCC, or POR?
   1. If possible, it would also be helpful to test this normal case while connecting POR to a separate output pin and including it in the scope shot. Seeing when POR goes high would indicate to us when we expect the start-up sequence to have completed.
2. Could you share how you are testing this, for example on an EVM, prototype board, etc.
3. Could you share the version of ICS you are using?
4. If possible, could you share a screenshot of the internal configuration of LUT3_0_DFF2?

If I have these details, I can try to replicate the issue. The obvious conclusion is that something is driving the pin low, but I'm not sure why that would be happening right now.

Best,

Malcolm

Hi Malcolm,

You wrote: (red text)

Could you see what happens if you connect the input of pin IO7 to a couple of different things, such as VCC, or POR?
If possible, it would also be helpful to test this normal case while connecting POR to a separate output pin and including it in the scope shot. Seeing when POR goes high would indicate to us when we expect the start-up sequence to have completed.

This means, I should burn special one and test. I will try later.

Could you share how you are testing this, for example on an EVM, prototype board, etc.

My writing environment;

Win11 PC - TPLD-PROG - TPLD1201-DGS-EVM

Programmed TPLD1201 is tested at:

TPLD1201-DGS-EVM(with burned TPLD1201) P2 - Our Functional tester ( to provide VCC to EVM )

Please refer also my previous post.

Of course, I remove all the jumper pin from TPLD1201 to EVM board circuit. And used J1 to connect EXT_VCC and EVM VCC.

Could you share the version of ICS you are using?

If possible, could you share a screenshot of the internal configuration of LUT3_0_DFF2?

At the same environment, here's another result:

      Pin Setting             Initial Output  External PU
IO7 Digital Output / NMOS OD         H           YES
IO6 Digital Output / PushPull        H           NO
IO5 Digital Output / NMOS OD         H           YES

IO6 and IO5 output normally. Especially IO5 goes high from VCC startup using the external PU. I think only IO7 has low output at the startup time.

At current, IO7's behaiviour is acceptable for us. But I want to know the reason.

Best,

Yasunori Okutsu

Hi Yasunori,

I would also like to know the reason!

I am going to test this out on my end and, if I am able to replicate the result, I will bring it to our system and design team to determine what is going on. So, I will get back to you either tomorrow or at the beginning of next week.

Best,

Malcolm

Hi Malcolm,

I see and will check my board again. Thank you very much.

Best,

Yasunori Okutsu