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SN54SLC8T245-SEP: Data Rate

Part Number: SN54SLC8T245-SEP

I am looking into the voltage translator: SN54SLC8T245-SEP. The datasheet only gives maximum data rate as 380Mbps. But I would like to get the specific data rates in Hz when VCCA = 0.9/1.2V and VCCB = 3.3V. Is there any way I can calculate this with switching characteristics? 

  • Hello Chris,

    We can use the following formula to estimate data rate: 1/tpd

    For VCCA = 0.9V and VCCB = 3.3V, tpd equals 9ns. This means the data rate would be 111 Mbps (typ).

    Regards,

    Josh

  • Hi Josh,

    Thanks for the response. I am relatively new to ASIC design and would appreciate some clarification.

    Could you explain how propagation delay is being used to derive the data rate in Mbps? My understanding is that propagation delay represents latency, not necessarily the maximum achievable data rate.

    For my design, I need to determine whether this level shifter is compatible with a specific interface, so I am looking for a more concrete way to determine the supported data rate at VCCA = 0.9/1.2 V and VCCB = 3.3 V. Is there a method to determine this from the datasheet (e.g., rise/fall times, minimum pulse width, or test conditions used for the 380 Mbps specification), rather than using an estimated value?

    Thanks in advance for your help.

  • Hello Chris,

    The estimation is derive from the minimum bit duration of the signal. For example, at 300Mbps, the minimum bit duration would be ~3.3ns. But again, this is an estimation as max data rate takes into account prop delay, input thresholds and output transition rate.

    The best way to determine max data is to test the part in your own system. If you can reach out to a TI representative, they can send some samples to you.

    All the test conditions we have used can be found in Section 6.

    Regards,

    Josh

  • Hi Josh,

    Thanks again for the response. It seems that the test conditions in Section 6 were based on a capacitance load of 15 pF, which gives us a propagation delay of 5 ns/4 ns at 1.2 Vcca. If the capacitance load increases to 50 pF, would it be acceptable to consider that the propagation delay would also be tripled?

    Also, is there any impact on the disable time and enable time with change in the capacitance load?

    Thanks,

  • Hello Chris,

    We are looking into this and will respond soon. Thanks!

    Regards,

    Josh

  • Hello Chris,

    Apologies for the delay. 

    The parameter that will be impacted the most is transition time (rise/fall time) which can lead to a different propagation delay value. Since we have not captured prop delay at 50pF, we cannot guarantee it will be 3x. However, you will see a higher propagation delay (>5ns) when operating at 50pF.

    Disable and enable time compares the timing between OE input vs output level (either switching from High to Low or Low to High). Since the transition time increases with higher load capacitance, the values for both disable and enable timing will also increase.

    Regards,

    Josh