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SN74LVC8T245: Output State During Power UP

TI-CSC
Genius 16385 points

Part Number: SN74LVC8T245

Hello E2E Experts, 

Please see the circuit below, in regards, to how we are using the SN74LVC8T245.  Data is input at B and output at A.  You recommend powering up the input (VB) before powering up the output (VA).  We are doing the opposite. The power sequencing on our board is such that VA (5V) comes up before VB (2.5V).  2.5V is generated from 5V.  The OE enable is referenced to VA (5V).  The pulldown (R405) has been removed.  We now have a 10K pullup on the OE to VA (5V) which is not reflected in the circuit below.  What is the state of the outputs at A while the VB (2.5V) comes up?  Are the outputs at A guaranteed tristated (high impedance) state until the VB reaches active level 1.65V, which is the minimum VCC level, even though VA is already 5V?

image (1).png

  • 0
    TI__Mastermind 43830 points

    Hello,

    Thank you for the detailed explanation.

    Since the /OE pull-down resistor has been removed and replaced with a pull-up resistor, the state of outputs A will remain high impedance even after VB is fully powered on. \

    The control inputs (/OE and DIR) are referenced to VA. With VA fully powered and /OE pulled HIGH, VB could be 0V or 2.5V, the output will always stay at Hi-Z.

    Regards,

    Josh