SN74LVC74A: CLR and PRE signal issue

ATHIRA K VINOD

Part Number: SN74LVC74A

Dear Team,

I have designed a frequency divider with SN74LVC74ANSR D Flipflop. The scheme and sim snippet is attached alongwith. The simulation model available TI website has been used for simulation in LTspice. The sim model has CLR and PRE. But in datasheet these are CLR' and PRE'(active low ). I am not getting correct output in board. Please do check and comment if any mistake in scheme.

6 months ago

0 Albert Xu1 6 months ago

TI__Mastermind 45845 points

Hi,

We generally do not support LTSpice simulations.

Further more, DFF simulations also almost always do not work correctly. Please see this FAQ: [FAQ] What is the default output of a latched device? (Flip-Flop, latch, register)

To honest, the simulation should not even be available on the product folder. I took a look at the model and it is from 2015 from our "WEBENCH Design Center" which isn't even from our Logic team.

My best recommendation is to use a built in DFF default model that is provided in LTSpice or any other simulation software you use.

0 ATHIRA K VINOD 6 months ago in reply to Albert Xu1

Prodigy 90 points

Dear Albert,

I understand the context. I will proceed with using the default model in LTspice.

Additionally, please ensure that the models available in TI’s product folder have been logically verified. If any of them are outdated, kindly mention this explicitly.

Logic

Logic forum

SN74LVC74A: CLR and PRE signal issue