SN74LVC1G373: need clarification.

Hello,

I assume the author intended the term "cleared" to mean that the latch was allowed to operate in transparent mode again (thus LE = HIGH), but it is a bit misleading in the terminology used.

I have always thought the terminology in D-type latches like the '373 was quite confusing. "LE = Latch Enable" sounds to me like a HIGH should activate the latch, but actually it is disabling the latch and allowing data to pass through.

To avoid misunderstanding, on page 13 of the datasheet (page immediately preceding the applications section you are referencing), the device functional mode table shows that LE being HIGH will allow a signal through, and LE being LOW will hold the previous state (Q0), which is the industry standard for the '373 D-type latch. See Nexperia's datasheet (page 4) or Onsemi's datasheet (page 2) for reference.

And on the same page, note that the applications section is not part of the device specification and TI does not warrant its accuracy or completeness:

pragash sangaran78 said:

I know you might feel my question is silly. I will ask anyway.

I do not find your question silly and will help as much as I can.

pragash sangaran78 said:

Is there any other part that consumes less current than SN74LVC1G373YZPR?

No, I'm afraid TI doesn't have another latch that has lower power than this single CMOS latch. If you get one and test it yourself, you will find it very difficult to measure the power consumption because it draws so little current -- most testers just read noise.

pragash sangaran78 said:

There are two types of current draw: operating current and quiescent current. my 1st prioty is quiescent current when the device is in ideal mode or non-operational because there is no input at D. 

There are indeed two types of power consumption in CMOS logic, we call them static and dynamic power. I have an app note that goes into great detail on this topic located here: https://www.ti.com/lit/an/scaa035b/scaa035b.pdf

What I have been referring to is the static power consumption of the device - ie how much it will draw when you are not switching the inputs. In most LVC family single gates the power is so low that you would never notice it unless you are counting individual nanoamps, or if you are running the system at extreme temperatures (ex: +125C).

The power draw when switching the inputs, the dynamic power, is determined by the power dissipation capacitance, which is explained in detail in the app note I linked above. If you're controlling an RF signal, it is likely that the power draw from this latch in your signal chain will be negligible. Most RF components draw enormous power compared.