Part Number: SN74LVC2G126
Hello,
I found an error in your Spice model for the SN74LVC2G126.
The error results in a divide by zero error when simulating the model.
Starting at line 186 of SN74LVC2G126.lib:
.SUBCKT LOGIC_TRI_STATE_OUTPUT_LVC_1i_AND_Tristate_CMOS_SN74LVC2G126 IN OUT OEZ VCC VEE
EROH NROH VEE TABLE {V(VCC,VEE)} =
+(1.65,112.5)
+(2.3,50)
+(3,37.5)
+(3,29.1666666666667)
+(4.5,21.875)
EROL NROL VEE TABLE {V(VCC,VEE)} =
+(1.65,112.5)
+(2.3,37.5)
+(3,25)
+(3,22.9166666666667)
+(4.5,17.1875)
There are double 'x' values of 3 in these two tables.
I assume the second line entry is meant to be 3.3.
I cannot make this model change using PSPICE for TI and run a simulation; as once changed, the edited model is treated like a 3rd party part and exceeeds the limititations of the free licence.
Can I be provided an updated model with accompanying .libsig
Regards,
Josel
