Part Number: TPS3823
- Device: TPS3823-33DBVR (Mass-produced project).
- Issue: The datasheet specifies a minimum watchdog timeout period T_tout of 0.9 seconds. However, on the failing board, the actual measured timeout period is approximately 710 ms.
- Failure Rate: This is an isolated/single-unit failure. This is the second instance observed over several months. Other boards from the same batch, tested under identical conditions, pass normally and meet the datasheet specification.
- Test Method: After the board powers up normally, the watchdog input (WDI) signal is manually shorted to GND to stop toggling. The time from the last WDI transition/short until the RESET signal triggers is then measured.
- VDD Behavior: During the entire test window, VDD remains stable and within the normal operating range. The issue is not triggered by a VDD dip or UVLO event.
- WDI Pin State: The customer confirmed this behavior is not related to WDI floating or entering a high-impedance state. Furthermore, a floating WDI would activate the internal watchdog timer, which would typically prolong or delay the reset, whereas the current issue is an early reset trigger (710 ms vs 0.9 s).
