We are planning to use a 74LVC244 to convert the output of an Avago HCPL5201 opto-coupler output to 3.3V logic levels prior to connection to an FPGA.
The output of the HCPL 5201 goes from 0.5V (logic low) to 3.1V (logic High) with a Vcc of 5V. The rise time is listed as 45 nsec typical or 17.3 ns/volt.
The input transition limit on the LVC244 is 10ns/volt.
By presenting a slightly slower than recommended signal to the LVC input, I assume we may get output glitches during the transition. That we can handle in the FPGA, since we are filtering this signal anyway.
However, we just wanted to make sure we would not cause damage to the LVC input by inducing oscillations/etc.
Do you believe we would damage the LVC244 input?
