CD4504B: CD4504B Front End Inquiry

Michael Ottenberg

Part Number: CD4504B

Internally on the CD4504B, what does the front end look like for each receiver? Is there any internal bias asserting (even weakly) a known state at each receiver input?

If the inputs are left open or floating while the outputs connect to an FPGA I/O bank, are the inputs required to be pulled up/down?

13 days ago

0 Sakthivel Ramesh 13 days ago

TI__Prodigy 460 points

Hello Michael,

We are still looking into the issue and will get back to you shortly

Thank You,

Sakthivel Ramesh

+1 Clemens Ladisch 12 days ago

Guru 327570 points

If there were pull-up/-down resistors, the specified input current would be larger.

You must not leave any inputs floating.

0 Sakthivel Ramesh 11 days ago

TI__Prodigy 460 points

Hello Michael,

As Clemens stated, external pull-ups/downs are required to maintain a high/low logic level input. You need a defined logic level to be able to use the device. You can not have inputs at high impedance state. There is no biasing that keeps the input at a known state by default

Thank You,

Sakthivel Ramesh

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CD4504B: CD4504B Front End Inquiry