Part Number: TXB0108
Other Parts Discussed in Thread: SN74AXC8T245, TXB0606, TXB0604
Hi team,
We are currently evaluating the W25Q32RVNJQ SPI NOR Flash with an FPGA using a Xilinx XMC-105 debug card.
The FPGA QSPI interface operates at 1.8 V, while the flash device is powered at 3.3 V. Therefore, we have used a TXB0108 bidirectional level translator between the FPGA and the flash.
Our test setup and observations are as follows:
System clock: Approximately 8 MHz
QSPI clock: 1 MHz
FPGA QSPI I/O voltage: 1.8 V
Flash supply voltage: 3.3 V
Level translator: TXB0108
Full 4 MB Quad Write: Passed
Full 4 MB Single Read and data verification: Passed
Quad Read: Data mismatch observed
The same firmware implementation was previously verified on silicon, where both Quad Read and Quad Bypass Read operations were performed successfully.
Therefore, the Quad Read command sequence and firmware implementation have already been functionally validated.
In the current FPGA-based setup, Quad Write works across the complete 4 MB memory range, and Single Read returns the programmed data correctly. The issue is observed specifically during Quad Read operation.
Could you please provide guidance on the following points?
Is the TXB0108 recommended for interfacing the W25Q32RVNJQ with a 1.8 V FPGA?
Are there any specific electrical or turnaround requirements for IO0 to IO3 during the transition from the command/address phase to the Quad Read data phase?
Are there any limitations associated with using an auto-direction level translator for Quad Read operation?
Can we use direction controlled translator like SN74AXC8T245 But with them I think we will face Issue with Direction controlling
Best Regards,
Aryan
