Hi,
I'm working on a design to replace an old +5V I/O standard CPLD to +3.3V I/O standard FPGA.
And, looking for voltage level translator to interface between +3.3V I/O (from FPGA) and +5V I/O (to peripheral IC and microcontroller).
Max datarate requirement for I/O is 60Mbps during communication between +3.3V I/O FPGA and +5V I/O microcontroller.
My concern is some of the I/O have 10K pull-up resistor tight to +5V.
Can I use TXS0108E?
Would 10K pull-up resistor impact TXS0108E VOL and VOH levels? From my understanding, this is only impact TXB type of translator.
If microcontroller I/O is using push-pull driver, can I achieve 60Mbps datarate? Or, the datarate will slowly increase from 2Mbps to 60Mbps?
Please advice.
Thanks..
Best Regards,
Atthen