I have a dilemma about this 12-BIT ASYNCHRONOUS BINARY COUNTER. In the datasheet is written : "A high level at the clear (CLR) input asynchronously clears the counter and resets all outputs low". Does it mean that as long as the CLR is on HIGH level the output gives all zeroes?
I need that all output bits go LOW on a rising edge of input signal which goes to the CLR pin...
In principle you can do what you said. The question is, how short can the pulse be.
Synchronous countes change their outputs after a clock edge. Asynchronous clocks don't have an external master clock signal. The typical async. clock is the ripple counter, where the change of each FF is taken as clock signal for the next FF. The advantage or ripple counters is simplicity and lower power consumption.
Their disadvantage... is that they are asynchronous. Have you ever seen a mechanical counter? Those that each wheel drags its neighbour? As you approach a situacion of "all nines", the counter looks uglier and uglier. Sometimes it is very difficult to understand what number is the counter showing
With ripple counters it is the same. Each FF of the counter is updated a bit later because of the chaining... and digital logic following the async counter can get confused.
These days, of very complex logic with thousands of registers interconnected, asynchronous logic is avoided whenever you can.
