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Logic level for 74lvc1g125

Eugeny Brychkov
Prodigy 60 points
Other Parts Discussed in Thread: SN74LVC1T45-EP, SN74AHCT1G125

Hello, I am going to use LVC125 inputs driven by the 3v3-powered signal, and its output should be +5v CMOS compliant.

I see from datasheet that I can power LVC125 from +5v. However with +5v power supply VIH voltage is defined as 0.7*VCC, which is 0.7*5=3.5V!

Will then 3.3v or below (let's say, standard TTL level when logical 1 is reliably recognized when input voltage is above 2.3V) be recognized as logical 1?

Thank you!

  • 0
    Mastermind 7395 points

    I am afraid the LVC125 will not be good for your application, but you could check the SN74LVC1T45-EP instead.

  • 0 in reply to Avi Chami1
    Prodigy 60 points

    Thank you!

    1t45 does not have output enable option... only direction. If there would be "1t44" stuff...

    The onvious what I can do is to use lvc125 + lvc_t45 but these are two devices. Is there anything you may suggest? Such a device in one package? 

    About application: I need to pass global clock signal from 3v3 device to 5v CMOS device(s). It should be done in specific circumstances (that's why I need /OE option), otherwise output should be tristated.

  • 0 in reply to Eugeny Brychkov
    Mastermind 7395 points

    Hi,

    The SN74AHCT1G125 has OE, TTL compatible inputs (vih=2V) and 5V outputs. Is this one OK?

    If it is for clock distribution, check the tpd also (dunno if it can be a problem for you)

    Best regards,

    Albert

  • 0 in reply to Avi Chami1
    Prodigy 60 points

    Cool, thank you. I think this is the one I need. tpd of 6ns is ok. hl and lh have equal timing so it is also ok.

    I connect its input to the fpga chip (3v3 output supply voltage). Can you advise please if having ahtc125 connected to the +5v can create abnormal currents at some conditions which may damage the fpga chip's input of output gate? I guess as 125's input pin is only-input pin, there should be no internal components which would expose current to flow between 5v and 3v3 through fpga pin, but we would better confirm that (as there's no schematic diagram of 125 in its datasheet).

  • 0 in reply to Eugeny Brychkov
    Mastermind 7395 points

    The device has a very high input impedance (input current max = 1uA), so there should be no abnormal currents into or from the FPGA output, but I understand your question, and a final answer can only be given by a TI employee.

  • 0 in reply to Eugeny Brychkov
    TI__Mastermind 46480 points

    The part will have a clamp diode to gnd and Vcc on the output pin and a clamp diode to gnd on the input..

    If the part remains powered there would be no current path. 

    If the 5V Vcc is powered off and there is 3.3V on the output then the part could backpower from the 3.3V.

    The input has back to back blocking diodes so it would not have this issue.

    attached example sch

    AHC inpout and output schematic.docx