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SN74AVC4T774 partial power down mode question

1351769
Intellectual 275 points
Other Parts Discussed in Thread: SN74AVC4T774

Hello,

Is it ok to pullup the DIRx and OE# pins to VCCB on the SN74AVC4T774 during partial powerdown? In my application, VCCA is 1.8V and VCCB is 3.3V and during partial powerdown VCCA is 0V.  Currently the DIRx and OE# pins are tied to VCCA since they are powered by it.  However, during partial powerdown, 3mA is drawn on the VCCB rail.  Should the DIRx and OE#, be pulled up to VCCB in this case although they are powered by VCCA to minimize current draw?  The 4T774 webpage references scea030a.pdf which indicates that this is ok (similar but different device) even though they are powered by VCCA.

Thanks.

  • 0
    TI__Expert 4705 points

    Hi,

    The SN74AVC4T774 has the Vcc isolation feature, which means when VccA is 0 while VccB is on, both ports are in the high-impedance
    state. so no need to pull up the OE# and DIRx to VccB.

    The reason caused the current draw may be you have the floating pins or tri-state pins on B side when VccA is 0 while VccB is on. could you please share your schematic with me or check you design by yourself to make sure no floating pin or tri-state pins for both your target input or output pins on B side.

    For this part, if you care about the current draw at tri-state , please pull up or pull down all the pins or drive them at High or Low state.

    any unclear, please let me know 

    BR

    Junjie