We are exploring a TI mux/demux part: http://www.ti.com/product/sn74cbtlv3257
The question is: when operating in demux mode where an input is connected to 1 of 2 outputs, what is the state of the unconnected output? Is it in high impedance?
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We are exploring a TI mux/demux part: http://www.ti.com/product/sn74cbtlv3257
The question is: when operating in demux mode where an input is connected to 1 of 2 outputs, what is the state of the unconnected output? Is it in high impedance?
I think so. You can see that on the timing diagrams on page 5. When the output control (combination of S and OE/) disables an output, the output goes to the 'Z' state, namely, high impedance.
After further review of the spec, I think it will work this way.
The figure shows how an output goes ‘disable’ with the load circuit attached.
The load circuit tends the output to go either high or low when disabled from an opposite state.
The IN OUT pins are very high impedance.
So when the unused output goes HIGH Z it will be pulled slightly one way or the other depending on the pins leakage current and system loading.