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Output enable on SN74AVC32T245

Vinayak Gokhale
Prodigy 10 points
Other Parts Discussed in Thread: SN74LVC1G240

Hello,

I hope I am posting in the right forum. We need to use this for our research. The output enable information seems a bit sketchy for me. The truth table says that the OE' is active low and hence, obviously, is connected to L. The description/ordering information (1st page, last paragraph) says that OE' needs to be connected to POWER through a pull up. It gives very little information about the pull up. Anyone have any ideas what it is trying to say?

Thank you

  • 0
    TI__Mastermind 46480 points

    Hi  Vinayak

      If you need the part to power up with the I/O's in high impedance then you will wan to tie the OE to Vcc through a resistor.

    If you dont care if the I/O's come up active them it is OK to tie the Oe low.

  • 0 in reply to Chris Cockrill
    Prodigy 10 points

    Thanks a lot for your help Chris.

  • 0 in reply to Vinayak Gokhale

    But what happens after VCC has finished ramped up? "Output Enable" is still high (tied to VCC via resistor) and outputs are disabled? Do I have to use some timing circuit to drive OE low after device initialization, when all input levels are correct and steady? Actually, I have such situation: I want to use SN74LVC1G240, inverting buffer. 5V VCC rises and stabilizes faster than correct input level becomes ready. How can I prolong 3-state output state of this chip for example 10ms after VCC ramps to +5V? 10ms is the time after which input level becomes valid. I am thinking about RC circuit (C on OE and VCC pins, and R on OE and GND pins). But what will happen on device power down? C is charged and will source current to OE pin with reference to VCC, when VCC rampes down. Could this demage the SN74LVC1G240? Does capacitor between OC pin and VCC rail will prolong Z state of the output?