I am questioning the following convention to see if it is common amongst the community.
For differential receive signals:
H of the signal is connected to the + of the receiver, and L of the signal is connected to the - of the receiver, results in an active HIGH signal at receiver output
L of the signal is connected to the + of the receiver, and H of the signal is connected to the - of the receiver, results in an active LOW signal at receiver output
For differential drive signals:
If active High signal is desired, present a logic 1 at the differential driver input. The differential driver + output will represent the H of the signal, and the driver - output will represent the L of the signal
If active Low signal is desired, present a logic 0 at the differential driver input. The differential driver + output will represent the L of the signal, and the driver - output will represent the H of the signal
Is this convention consistent with what is intended in industry for Active High and Active Low signals? Does it really matter in the end, since it's all interpretation of signal levels, especially when an end target is an FPGA?