Hello,
i've built a pcb based on ADS1675REF board.
Actually board does not behave the way i was expecting, analyzing signals on PCB to see if something's wrong i've discovered that applying a cmos clock signal to ADS1675 ADC through SN74AHC1G32 results in a half peak-to-peal swing range signal at output of OR gate in respect to signal applied ad its input.
The schematic is at page 20 of 23 of the ADS1675REF User Guide. Just i want to know, Is that a wrong behavior? Maybe the OR port is faulty? What is the reason the OR gate is placed on path through pin 55 of ADC? it realizes a sort of buffer?
Thanks in advance.
MR