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SN74AVC4T245

George Biner (Arrow)
Intellectual 705 points
Other Parts Discussed in Thread: SN74AVC4T245

 Hello:  I am forwarding questions from my customer regarding the SN74AVC4T245: 

>>>>  I have questions regarding the SN74AVC4T245 buffer:

  1. Suppose the DIR pin is low (data A ß B), VCCA is powered from 2.5V and VCCB is floating.  Will pins 1A1, 1A2, 2A1, and 2A2 be in a high-impedance state even if OE is low?
  1. What about when VCCB is connected to GND?
  • Suppose the DIR pin is high (data A à B), VCCA is floating and VCCB is connected to 2.5V.  Will pins 1B1, 1B2, 2B1, and 2B2 be in a high-impedance state even if OE is low?
    1. What about when VCCA is connected to GND?
  • Suppose both VCCA, VCCB, 1DIR, and 2DIR are floating and 3.3V is applied to pins 1A1 and 2B1.  Are pins 1B1 and 2A1 in a high impedance state even if OE is low?
    1. What about when VCCA, VCCB, 1DIR, and 2DIR are connected to GND?

For all of the scenarios above, will damage occur to the SN74AVC4T245 buffer?   >>>>>>

thanks, George Biner, Arrow FAE Los Angeles

  • 0
    TI__Mastermind 30310 points

    1. VCCA = 2.5V, DIR = LOW (data from B to A)

           a) VCCB floating --> Need to verify with expert

           b) VCCB = GND --> All ports are in high-impedance mode

    2. VCCA = 2.5V, DIR = HIGH (data from A to B)

           a) VCCA floating --> Need to verify with expert

           b) VCCA = GND --> All ports are in high-impedance mode
    3.  All inputs in same state (VCCA, VCCB, DIR1, and DIR2)

    a)  floating --> Need to verify with expert

    b) GND -->  All ports are in high-impedance mode

    See datasheet for verification of (b) answers: "The VCC isolation feature ensures that if either VCC input is at GND, then both ports are in the high-impedance

    state"

    I will get an answer from an expert on (a) questions because I do not know for certain what the input structure to VCCA and VCCB are that would determine a GND state in the case of the node floating.

    -Brian

  • 0 in reply to Brian Berner
    TI__Mastermind 30310 points

    Here is the input from an expert on the subject:

    1. a) VCCB must be tied to GND to ensure that A ports are Hi-Z (part in isolation mode). If VCCB is non-zero, there will be a threshold where the part leaves "isolation" mode and the A ports are "Enabled" as outputs

    2. a) VCCA must be tied to GND to ensure that B ports are Hi-Z (part in isolation mode)

    3 a) Without power, all ports will obviously be in a Hi-Z state, but it would still be a good idea to ensure that either VCCA or VCCB is held to GND

    With the information I have, these scenarios are all hypothetical in that "floating" is not a word often used to describe power supplies. If there is some way that VCC is held at >1V for an extended period of time (capacitance on the power bus), then for that amount of time the part will not enter isolation mode as it would when said VCC is being forced to GND.

    If the system conditions could be explained then maybe I would be able to answer with more certainty. Please reply with any follow up questions/info or "Verify" the answer if it is sufficient.

    -Brian