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SN74LV123A Behavior

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Genius 4220 points

Hi,

I'd like ask about the description in D/S as follows and the behavior of the attached circuit,

1. the description in D/S page2,

"During power up, Q outputs are in the low state, and Q outputs are in the high state."

"During power up" means that  the VCC voltage is between 0V to 2.0V, is it right?

2. about the attached circuit,

  the trrigger to start oscillation is detecting 1B Low to high edge.

 When VCC dropped to around 1V , then back to 3.6V, the circuit sometimes doesn't start oscillation.

I think it's because that  the input residual charge affects the internal circuit bihavior,

Is there some possibilities that  the input residual charge affects the internal circuit bihavior like this?

thanks

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