Hi,
One of my customers is implementing a PCI interface with a Xilinx Spartan-6 FPGA.
As this is not 5V tolerant, he is adding the sn74cb3t16210 as level shifter between the connector and the FPGA.
But we have some questions about the trace length, and how this should be interpreted.
I see that signals must have a max trace length of 1.5" and the clock 2.5" +/- 0.1".
Should we calculate this between pci connector and level shifter?
What about the interface level shifter to fpga?
Or can we not put this level shifter, if we want to comply with the PCI spec?
Thanks
Johan