Dear Sir,
I am Vijetha H.N from iWave Systems Technologies, Bangalore, India.
We are using 4 number of DSPs of part number TMS320C6457CCMH2 in our design. For this DSP, we need to give 60MHz as Core Clock and 66MHz as DDR referance clock as mentioned in the "TMS320TCI6484 and TMS320C6457 DSPs Hardware Design Guide" (datasheet number: SPRAAV7B, Table 2 in page number 8). It is also mentioned that the rise and fall time for Core clock and DDR Referance clock are 50 ps-350 ps each. We use LVDS logic clocks (differential clocks) for core and DDR referance clocks.
We use oscillators FN6000036 and FD6600015 for 60MHz and 66MHz respectively. Since we need to feed 4 DSPs, we need to use 1:4 Clock buffer (LVTTL input and LVDS output). Currently we have selected SN65LVDS105 for this purpose. Please let us know whether SN65LVDS105 can be used as Clock buffer (meeting all the timing requirements).
Note: Its mentioned that " The intended application of this device and signaling technique is for point-to-point base band data transmission over controlled impedance media of approximately 100Ω. This is particularly advantageousindistributionorexpansionofsignalssuchasclockorserialdatastream." in the Datasheet of SN65LVDS105.
So please make it confirm that can SN65LVDS105 be used as clock buffer for the above requirements of DSP.
Looking for your response....
Regards,
Vijetha H.N
Hardware Designer
iWave Systems Technologies,
Bangalore - 560076,
India
