Hi,
after reading the data sheet some aspects of the SN74LV8154 remain unclear.
- How do I reset the counters? In the timing diagram on page 2 it looks like the counters are reset only on the rising edge of CCLR. I guess that's not the case. Later in the Specs there is a minimum setup time of CCLR before any CLK. What happens if that setup time is violated? Can somebody explain that signal?
- If CCKA, CCKB and RCLK are connected, can there be internal race conditions? Which value is clocked into the output registers? Is the timing diagram on page 2 correct, where the value "3" appears on the output? Which RCLK-edge brought that out?
Thanks
