The questions below pertain to the use of the 74LVC1G125 and the 74LVC1G126 applied where it is necessary to have a single buffer (w/ tri-state control) to isolate logic between power domains. The power domains are not sequenced and they can come up or down in any order. The questions below are specific to the time when the buffer is not powered but its output is connected to a circuit that could be powered.
The basic circuit configuration is (see photo uploaded):
- input is tied to ground, OE is pulled via a resistor to the same supply as the chip power domain
- the output is pulled to a separate supply via a resistor
Questions are:
1, If the buffer is not powered yet, what’s the inputs’ state? True hi-impedance or clamped to GND thru a diode?
2, If the buffer is not powered yet, what’s the output’s state? True hi-impedance or clamped to GND thru a diode?
3, If clamped to GND, can you recommend alternatives like a single-bit OC/OD buffers with EN control?
