level shifter output 0 toward CPLD,CPLD also output 1 toward level shifter, will this contention damage the IO port

koushan tao

Other Parts Discussed in Thread: SN74ALVC164245

I have a CPLD (3.3V) and a CPU (+5V), the level shifter SN74ALVCH164245 is between them

CPLD(3.3V)--A Port of level shifter ---B Port of level shifter---CPU(5V)

At first CPU wirte data "0" to CPLD,a  pin of the level shifter is outputing a "0" to CPLD

then CPU read data, the CPLD change direction quicker than level shifter,

CPLD output a "1", at this moment , the direction of level shift has not turn over,it is still outputing a "0", so there is a contention, there is a short cut on this pin, "0" is connected to "1"outputed by the CPLD , will this damage the IO port ? Can it work safely for a long time?

I heard some IC designer say that the IO pin often has pullup and pulldown resitors and clamp diodes inside,it will limit the current and voltage, so it is safe. He also says these kind of contention is very common, IC designers have considered it. Is it true?

best regards

koushan

over 11 years ago

0 Wei Lang over 11 years ago

TI__Expert 6430 points

Hi, Koushan

At page 3 of SN74ALVC164245 datasheet, you will find the information of Input Clamp current. its max value is 50mA. When CPLD outputs "1" and 245's I/O keep '0',the current will flow though the I/O. If the drive current of the CPLD is enough large, the SN74ALVC164245 will be damaged. If the drive current of the CPLD is weak, its high output will be pull down. It is better to delay the signal in CPLD.

Thanks

Lawrence

Logic

Logic forum

level shifter output 0 toward CPLD,CPLD also output 1 toward level shifter, will this contention damage the IO port