Hi you guys
I'm planning to develop a Backplane which contains about 21 slots (each slot includes 6 FPGA! so the total number of FPGAs is 126 !!)
I have good experiments in designing and developing FPGA boards but I never worked on a Backplane !
Could you guys kindly help me with some information so I know where to begin ?
I will attach some picture of what I have in mind. For now I should tell you there is 64 bit Data Bus between this FPGAs
For example I want to reach at least 20 MByte/s . Is it possible?
What buffer or signaling or technology should I use ?
After I searched I figured Texas Instruments has some products related to this area. Is there a ready design to begin ?
