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How to setup JK flip flop cautiously?

Hi

the circuit is controlling a power distribution unit.  i have several possible FFs, a 74112  74114  74109  74107?  apart from their types, S, LS or AS, power and speed are not factors.

problem:  JK ff triggers before being clocked.  power distribution comes on spontaneously

circuit:  instead of a relay i selected a JK ff wired so that j and k are 1 and 0.  when clock happens i just want it to toggle, thats it..   apparently there is instability such that  the ff toggles by itself.   i put the same ff onto a breadboard and confirmed the input states on the pins.  the switch that drives the clk input is simply a 22k pulled up line thats touched to gnd.  

question:  any known solutions for this?  one idea was to wire up some delay so that the CLR line is held low for a while after powerup, 1 second should be okay.    i have a  74ls14  schmitt inverter and could put a capacitor in the circuit.  

possibly a 100k pullup and 10uF cap to gnd on one inverter then that feeds a 2nd one.  so after the 2nd one as the circuit comes up that line, CLR stays low until the 1st inverter changes.    the circuit needs to be reliable 

im guessing at the R and C values any help is greatly appreciated, thanks