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Level Translator for System Clock

Periyasamy Balasubramanian
Prodigy 215 points
Other Parts Discussed in Thread: SN74AVC1T45

Hi,

I"m getting System clock from the base board to clock the FPGA in my daughter card. The system clock is ~166MHz with voltage level of 1.8V or 3.3V (programmable in base board). I need to interface this SYStem CLK to GCLK of FPGA port which is having VCCIO of 2.5V.

Please suggest a TI device to support two possible level translation combination without any delay

1. from VDD1(1.8V) to VDD2(2.5V) without delay,

2. from VDD1(3.3V) to VDD2(2.5V) without delay

Kindly check & suggest TI part ASAP.

Thank you.

  • 0
    TI__Expert 6430 points

    Hi,

    SN74AVC1T45 may meet your requirement. This part supports level translation between any of the 1.8V, 3.3V and 2.5V. However, if signal translate to 2.5V, the max data rate is 320Mbps at 15pF load. When transfer signal is clock, the max clock frequency is 160MHz at 15pF. Thus, please run some simulations with SN74AVC1T45 IBIS model and your system real load to verify the solution. As for delay, some simulations are needed to make sure real delay time in your system.

    BR

    Lawrence

  • 0 in reply to Wei Lang
    Prodigy 215 points

    Hi,

    Please clarify the following,

    I would like to connect 1.8V to VCCA & 2.5V to VCCB of SN74AVC1T45 for my above said requirement. & I would like to use 3.3V tolerant IO feature of SN74AVC1T45 on VCCA side, so that 1.8V & 3.3V clock on VCCA(1.8V) side input shall be translated into 2.5V level. Kindly confirm whether shall i use this overvoltage tolerant feature for clock (or) whether you recommend to use 1.8V on VCCA for 1.8V clock & 3.3V on VCCA for 3.3V input clock.

    Please clarify.

    Thanks.

  • 0 in reply to Periyasamy Balasubramanian
    TI__Expert 6430 points

    Hi,

    The latter is correct (to use 1.8V on VCCA for 1.8V clock & 3.3V on VCCA for 3.3V input clock).

    If VCCA is powered at 1.8V, the minimum of high-level input voltage is 1.17V and maximum of low-level input voltage is 0.63V. If VCCA is powered at 3.3V, the minimum of high-level input voltage is 3V and maximum of low-level input voltage is 0.8V.

    BR

    Lawrence

  • 0 in reply to Wei Lang
    Prodigy 215 points

    Hi Lawrence,

    Thanks for reply. In my case, output from base board is LVCOMS which is having

    [VoLmax 0.4V, VoHmin 1.5V for 1.8V clock Out] [VoLmax 0.5V, VoHmin 2.6Vfor 3.3V clock Out] (attached below)

    [ViLmax 0.63V, ViHmin 1.17V for 1.8V clock In]  [ViLmax 0.8V, ViHmin 2.0Vfor 3.3V clock In]

    I think noise margin may not be the problem. Please let me know your view on this & now can i use only 1.8V on VCCA for 1.8V clock in & 3.3V clock in

    Kindly clarify.

    Thanks.

  • 0 in reply to Periyasamy Balasubramanian
    TI__Expert 6430 points

    Hi,

    I agree with you that noise is not problem. The input voltage of SN74AVC1T45 is from 0 to 3.6V (on page 4 at its datasheet). Thus, the port can pass 3.3 V clock when power is 1.8V.  Please make sure the low level input voltage is less than 1.17V when 3.3V clock is used in the base board even though this parameter is qualified at datasheet.  

     BR

    Lawrence