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SN74AVCH4T245PWR-using active Bus hold and output enable function for latching

Anoop Joshi
Expert 1125 points

Hi,

I'm using SN74AVCH4T245PWR IC for a project, and one of the 4 data lines (A1,B1) is to be used for a bi-directional signal between a test chip and an FPGA. VCCA=VCCB=3.3V. I referred to the "SCLA015" app note, and most of my doubts were cleared, but I had a few more queries regarding the bus hold circuitry functioning here,could you please provide some help with them:

1.First let's assume data is transmitted from A1 to B1. I force logic 1 on port A1 first (1DIR being high and 1OEZ being low, ie, output is enabled) and it appears on B1. Now if I make 1OEZ high(thus disabling the outputs), by bus hold operation,will logic 1 still be maintained on bus B1, irrespective of the signal that is applied on A1 and signal on 1DIR as long as 1OEZ remains high(assuming B1 isn't driven from the opposite side)? Basically I'd like to know if the combination of bus hold circuitry and OEZ function used as a sort of latch to latch the last input on A1 on port B1 by making OEZ high.

2.If yes, the logic 1 on bus B1 that is held by bus hold can reliably drive another buffer connected to B1 as long as the buffer draws in less than 100uA?

3.Now if I make 1DIR low(such that data should flow from B to A), and enable the output by making 1OEZ low, now the external driver connected to B1 has to sink at least 500uA, if it were to transmit a logic 0 to port A1 right?

Thanks,

Anoop

  • 0
    TI__Expert 6430 points

    Hi Anoop,

    I agree with your first comment and third comment.

     As for second comment, I am not clear the 100 µA.  Where is from?  If it is IBHL or IBHH, I will clarify it. When VIH is 2V the IBHH is 100µA. It is not driver current. It is just measured result when VI is at different value. This value is just valid when VI is present.

    Thanks

    Lawrence

  • 0 in reply to Wei Lang
    Expert 1125 points

    Hi Lawrence,

    Thanks a lot for the reply! Actually, in the second comment, I was assuming that port B1 is driving some other buffer(let's call it "X"), ie, the output on port B1 is the input for some other CMOS buffer stage "X". Ideally that "X" input would draw only a few 10uA leakage current from port B1. Actually my requirement is that, let's say the value on B1 is held at logic 1 by the bus hold circuitry. Then it will be acceptable as a valid logic 1 for the "X" input as long as the current drawn is <500uA right? (I'm sorry In my previous post I wrongly referred to the 100uA value which is actually the IBHL/IBHH)

    Also, assuming my logic high level is 3.3V at B1, and the "X" input draws a worst case input leakage current of 450uA from B1, could you please tell to what voltage the 3.3V logic high voltage at B1 might drop to(I would like to know if it will still be greater than VOHmin so that it may be detected as a logic 1 by "X")?

    Thanks,

    Anoop

  • 0 in reply to Anoop Joshi
    Expert 1125 points

    Hi Lawrence,

    Thanks a lot for the reply! Actually, in the second comment, I was assuming that port B1 is driving some other buffer(let's call it "X"), ie, the output on port B1 is the input for some other CMOS buffer stage "X". Ideally that "X" input would draw only a few 10uA leakage current from port B1. Actually my requirement is that, let's say the value on B1 is held at logic 1 by the bus hold circuitry. Then it will be acceptable as a valid logic 1 for the "X" input as long as the current drawn is <500uA right? (I'm sorry In my previous post I wrongly referred to the 100uA value which is actually the IBHL/IBHH)

    Also, assuming my logic high level is 3.3V at B1, and the "X" input draws a worst case input leakage current of 450uA from B1, could you please tell to what voltage the 3.3V logic high voltage at B1 might drop to(I would like to know if it will still be greater than VOHmin so that it may be detected as a logic 1 by "X")?

    Thanks,

    Anoop