I’m looking at a design where the SN74LVTH2245 is used as a buffer between a processor data bus and an I/O bus. The direction control and output enable being driven by a CPLD. Both signals are changing on the same edge of the CPLD clock. The data sheet does not specify the delay from DIR to A or DIR to B. Do we have any data for the DIR to A / DIR to B prop delays?
Thanks!
