It is possible that the circuit being driven by the 3.3V to 5V level translatior acting as a buffer is too fast. We always see effects as if there was an extra clcok pulse detected by the receiver ckt. We need to explore how to slow down the output transition times. It is not quite possible to add a series resistor at this time & in this assembly. So the question is: will Tr & Tf slow down by loading the outputs with capacitor alone? If so, what is the largest cap we can add?
Our data rate is quite slow so power dissipation is not going to be the issue but max peak current capability will if capacitive load will cause a slow down of the transitions.
we would like to know!
-robin
