• State
  • Locked Locked
  • Replies 1 reply
  • Subscribers 20 subscribers
  • Views 367 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Input level for the SN65LVDS1DBV

Scott Siclari
Prodigy 15 points

I am trying to use the SN65LVDS1DBV to translate a 'clipped sine wave', which is a 0 to 1V psuedo-square-wave to translate to an LVDS input to a DAC Clock. Can I achieve this with this part and how? Do I need to bias the input to the part & at what level. I know the  part works with a CMOS level because that is what I have now, but I want to try a new reference clock that only has this lower level output.

  • 0
    TI__Expert 6430 points

    Hi Scott,

    SN65LVDS1DBV is one part of Amplifiers and High-speed PHY portfolio.  The engineers who answer questions in High speed interface Forum are experts in SN65LVDS1DBV .Please ask help from ‘High speed interface Forum'.

    Thanks

    Lawrence