hi,
we want to monitor two supply voltages (U1, U2) of an ASIC / mcu. via a respective power-on reset (POR).
Once both voltages i.O. are oki and the remaining time has expired, then the AND gate of the reset should show high level at the ASIC / mu.C.
The AND gate is supplied with V1 = 3.3V.
The ASIC / mcu recognizes a RESET pin from a high 0.7 * U1.
Since the ASI has a supply less than 1V, this lead to the following question:
How an error occurs when switching on and when the power supply voltage of the AND gate is less than 1.65 V, to ensure that the output of the AND gate low as soon as at least one of the inputs is low?
How the AND gate is constructed internally?
regards
kamal
