I have to add a short (2-12 nsec nominal) delay between two channels of logic driven by a single TTL source. I am hoping to do this by applying the input trigger to a SN74LVC3G34 triple buffer chip with the gates wired in series. I can then select between no delay, and the delays from 1,2, or 3 gates with a jumper. The output of this selection would drive one of the two channels in the system, providing a time delay between the channels.
The device i am making is a precision pulse generator for a fast laser system. One channel has a precision variable delay of up to 20 nsec, in 10 psec steps, while the other channel has a precision short pulse generator (200 psec). The precision (fast) parts of the circuit are implementted in LVPECL. The TTL trigger signal and the delayed version of it (using the gates as described above) are converted to LVPECL in a dual LVTTL to LVPECL translator.
I am not concerned with the actual Tpd through the gates, which is speced at 1.5 to 4.1 nsec at 3.3V (the operating voltage). This is a convenient "lump" of time to offset the channels. We need this delay to compensate roughly for optical propagation time in fibers, to get the two channels overlapped enough that the variable delay is operative, so rough lumps of time of 2-4 nsec are fine.. I AM very concerned about how the actual Tpd (whatever it might be) will vary as a function of temperature. The two pulses generated in the two channels are ultimately overlapped in a fiber coupled optical system, with a tolerance of +/- 200 psec or less. Getting the correct overlap is easy, but once established, it cannot drift much. Thus I need to get a solid understanding of how Tpd varies with temperature. The device is a piece of laboratory instrumentation and will probably not vary by more than +/- 10C in use, but the internal temparature of the box may be warm.
Any help in understanding this issue is greatly appreciated.
Michael Jefferson
Force 12 Systems
