SN74CB3Q3306 package pin out differential pair layout question

Mitchell Kary

Other Parts Discussed in Thread: SN74CB3Q3306

Hi,

The package pin out for the SN74CB3Q3306 seems to create a clumsy layout for getting differential pair traces in and out of the IC. I have a 1 GHz LVDS pair on pins 2 and 5 and pins 3 and 6. Is there a suggested PCB trace arrangement or perhaps a alternate part?

-Mitch

over 11 years ago

0 Chris Cockrill over 11 years ago

TI__Mastermind 46480 points

We do not have a switch that will do 1Ghz. The CB3Q will only pass 500Mhz. Here is one that might be layed out better but max frequency is 300Mhz

TS5A2066

0 Mitchell Kary over 11 years ago in reply to Chris Cockrill

Intellectual 630 points

Chris,

I meant to say in my opening post that the signal is 1Gbps LVDS signal, not 1 GHz (analog).

That said, even if I am trying to pass a 500 Mbps LVDS signal, how can one route to the pins maintaining a controlled impedance of 100 ohms with that pin out? Do you have any examples of the switch being used in a LVDS application such as a TI evaluation board?

-Mitch

0 Chris Cockrill over 11 years ago in reply to Mitchell Kary

TI__Mastermind 46480 points

I dont know of any examples or EVM's. Hopefully there is someone on this web site more familiar with this applications

Logic

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SN74CB3Q3306 package pin out differential pair layout question