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Pd spec for CD74HCT14

Philip
Expert 1510 points

Other Parts Discussed in Thread: CD74HCT14

Hi there, 

Do you have the Power Dissipation (Pd) spec for below different package Hex Inverting Schmitt Trigger Logic?
CD74HCT14E (PDIP)
CD74HCT14M96 (SOIC)

I could not find this information inside the datasheet.

Thanks.

  • 0
    TI__Mastermind 46480 points

    Here are the thermals

    Package

    Die Size
    (mils)

    Pad Size
    (mils)

    Low or
    High K

    Data
    Source

    Tja

    Pjt

    Tjc

    0 LFM

    150 LFM

    250 LFM

    500 LFM

    0 LFM

    150 LFM

    250 LFM

    500 LFM

    14N

    49 x 50

    60 x 60

    High

    Model

    79.7

    75.0

    72.8

    70.0

    44.55

    47.79

    48.46

    49.46

    63.5

     

    Package

    Die Size
    (mils)

    Pad Size
    (mils)

    Low or
    High K

    Data
    Source

    Tja

    Pjt

    Tjc

    Tjp

    Tjb

    0 LFM

    150 LFM

    250 LFM

    500 LFM

    0 LFM

    150 LFM

    250 LFM

    500 LFM

    14D

    63.3 x 126.8

    90 x 150

    High

    Model

    72.4

    51.1

     

  • 0 in reply to Chris Cockrill
    Expert 1510 points

    Hi Cris,

    Thanks for your reply.

    I see there are missing information on package 14D for Tja and Pjt, can you advise?

    And is there any application note which I can refer for this thermals details?

    Please do kindly advise, thanks.

  • 0 in reply to Philip
    TI__Mastermind 46480 points

    Sorry about that. Here you go

    Package

    Die Size
    (mils)

    Pad Size
    (mils)

    Low or
    High K

    Data
    Source

    Tja

    Pjt

    Tjc

    0 LFM

    150 LFM

    250 LFM

    500 LFM

    0 LFM

    150 LFM

    250 LFM

    500 LFM

    14D

    32 x 37

    70 x 70

    Low

    Model

    133.5

    106.0

    97.3

    87.0

    20.85

    23.05

    23.59

    24.49

    53.7

    16D

    44 x 65

    90 x 90

    Low

    Model

    111.6

    90.3

    83.0

    73.9

    5.75

    7.81

    8.33

    9.20

    38.4

    8D

    62 x 80

    72 x 90

    Low

    Model

    165.5

    126.2

    113.5

    97.7

    5.49

    8.25

    8.92

    10.01

    42.4
  • 0 in reply to Chris Cockrill
    Expert 1510 points

    Hi Chris,


    I noted you provided me some data for both 14N (PDIP package) and 14D (SOIC package) as below.

    May I know how is the power dissipation (Pd) derived from below data? Can you kindly advise?

    Is there a different spec between a High K and Low K board? What you have shown me is only High K for 14N and Low K for 14D.

    Please do kindly advise, thanks.

  • 0 in reply to Philip
    TI__Mastermind 46480 points

    Hi Philip

      I normally will send the High K data because that is what customers prefer. In this case there was not any data shown for the 14D high K.  The High K and low K will be very close.

    PD formula   PDISS(MAX) = ( (TJ(MAX) − TA(MAX)) / θ(JA) )

  • 0 in reply to Chris Cockrill
    Expert 1510 points

    Hi Chris,

    I have some additional question.

    Based on CD74HCT14 spec, θ(JA) spec for 14N PDIP package is 80oC/W and 14D SOIC package is 86oC/W.

    And based on your PD formula  PDISS(MAX) = ( (TJ(MAX) − TA(MAX)) / θ(JA) ), does it mean:

    For 14N PDIP: PDISS(MAX) = (150-25)/80 = 1.5625W and

    For 14D SOIC: PDISS(MAX)= (150-25)/86 = 1.453W?

     

    And can you help to advise how PDISS(MAX) co-relate with the information that you provided earlier on Tja, Pjt and Tjc? Please help to advise, thanks.