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LVC2G04 delay skew specification

In my application I need to invert 2 signals under the same operating conditions. I can tolerate delay, but I have a strict requirement on the skew between these signals. It seems obvious to me that the worst case skew is equal to tpd,max - tpd,min for a single inverter. This assumption is safe, but if both inverters are on the same chip (LVC2G04), the skew is almost certainly grossly overestimated (and outside my requirements).

Is there a channel-to-channel delay skew specification on the LVC2G04 ?

Is perhaps the LVC2G04 internally constructed with two LVC1G04 chips ?