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looking for a pll chip for fm demodulation

Dongkyu Kim
Prodigy 20 points
Other Parts Discussed in Thread: CD74HCT4046A

Hello.

I'm using the CD74HCT4046A as fm demodulation.

But I think it doesn't satisfy my requirement.

I'm trying to demodulate the signal(10MHz carrier freq, ±5MHz freq deviation and 500kHz modulation freq.)

I think that center freq of PLL is related with the carrier freq and freq lock range is related with the freq deviation. However I can't find any information about the modulation freq. So, there is difficulty to find the proper pll chip.

If anybody know the proper chip for my requirement or how to check the modulation freq from the pll datasheet, please answer this question.

Thank you

  • 0
    TI__Mastermind 46480 points

    Hi Kim

     I am not an expert on these part but I do have some appnotes I can send you. We have an newer version of the PLL that has better specs . SN74LV4046A.  I hav attache an appnote for the part you are currently using.

    Pll TI.pdf
  • 0 in reply to Chris Cockrill
    Expert 1040 points
    Hi Kim,

    It is a classical ANALOG PLL applciation, but a qiute critical from some aspects.
    I think you should consider/re-check the followings:
    1. XOR type phase detector should be used. It acts like an overdriven balanced mixer (classical) phase detector. This detector ensures the VCO runs on center freqency if no input signal, and have higher noise immunity. Digital memory detector (PFD) can be used only for synthersizers.
    2. Since PLL is a feedback system and it yields similar transfer function like an RLC low pass filter (second order delay element). However, not for voltages but for phase/frequency changes. Your application requires higher bandwith since fc=10MHz and delta f=5MHz are quite close to each other. So, The loop natural frequency (fn) should be simliar than max freq deviation->when loop fiter calc. And, loop damping (D) should be 0.5..1 for optimal operation.
    The freqency deviation contains the information about the INSTANTENEOUS modulation sig amplitue, so it should be passed by the "LPF".
    3. the analog PLL develops the VCO tuning voltage from a remained phase errror->this must be lower than 90 degree in the 5MHz deviation, otherwise the loop will loose the lock (thus, the phase error changes from 0 to 180 in the entire tracking range, and it is 90 degree at center frequency).

    I recommend to read NSC/TI appnote AN-46. It is very good text on subject of analog PLLs. Equations can applied for 4046 if XOR PD is used. For sinusoidal FM detetction Fig 6 helps to determine loop natural frequency (bandwidth) when fdev, fmod and damping given. Basic tradoff to ensure peak phase error 1 rad (57 deg) under all condition (leave 33 degree for noise).

    Other remarks:
    in your application a loop filter with high cutoff freq needed (when properly design, this will result) and cannot attenutate harmonics and 2*f0 VCO components effectively.
    If possible, lowering f dev from 5MHz to 1MHz. Of course, it reduces the recovered mod signal level, but the loop will be more robust and linarity would be improved (HC4046 VCO does not have so good linearity in the full control range). And use an additional filter for recovered signal with cutoff fc=500Khz, using an operational amp.
    I think 4046 is a good choice but the system paramaters are not so well.