Logic

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LSF0102 Level-Translation Problem

Kazuhiko Ogawa

Intellectual 985 points

Other Parts Discussed in Thread: LSF0102

Hallo,

Our customer asks the LSF0102 Level-Translation Problem as below.
They use the attached schematics circuit.
But they can get the following output level clock signal.
High level = 1.15V (almost OK)
Low level = 0.8V (Not acceptable)
Could you please advise me how to solve the higher low-level (0.8V) and get proper 0V – 1.1V clock output?

Best Regards,

Kazu Ogawa

over 11 years ago

0 Wei Lang over 11 years ago

TI__Expert 6430 points

Move to SLL logic forum.

0 Chris Cockrill over 11 years ago in reply to Wei Lang

TI__Mastermind 46480 points

this has been answered off line but here are the suggestions.

since it looks like they are only goin o direction they should remove R235. Put a short in place of R237.

and they may need to increase the value of R222.

0 Kazuhiko Ogawa over 11 years ago in reply to Chris Cockrill

Intellectual 985 points

Chris-san,

The customer was able to fix the problem by the way of your advice.

Thank you so much.

Best Regards,

Kazu Ogawa