cascode 74hc590

According to the schematic diagram in the data sheet, the RCO output just decodes all counter bits high, and does not also have the clock ANDed into it. So you should connect this to the count enable (CCKEN) of the next part, and run the clock (CCK) to both parts in parallel. Note that the counter itself is a ripple-carry counter. I would not suggest cascading more than two of these unless your CCK is running quite slow due to the long delay in generating RCO. Note that you could also use RCO to clock the next stage in ripple carry fashion. This would result in more delay to the highest bit in the chain but could allow the counter to run at a higher CCK frequency. The down side to this is that the highest bit might change after the next CCK edge, so you'd need to gate off the input clock before capturing the count in the output register in order to reliably read the current count.

By the way, this is a really old part. You could do the work of two or more of these in a small CPLD that runs many times faster and doesn't need to resort to ripple carry to run at high speeds.