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Interfacing with ICs that are Powered Down

Larry Johnson
Intellectual 320 points
Other Parts Discussed in Thread: SN74LVC2G17

I have a PDF drawing showing 2 SPI devices connected to a MSP430 microprocessor using six 74LVC2G17 gates as buffers for the CS1, CS2, SCLK, and SI input signals. Each SPI device and it's associated 3 buffers are connected to a switched 3.3v power supply. During normal operation the 2 SPI devices and their buffers are powered off. As needed one or both SPI devices (& their buffers) will be powered up and sent SPI commands, then powered down.

I wish to know if the 74LVC2G17 buffer will provide isolation to the inputs when it's VCC , it's outputs and its load are powered off. Also is the 74LVC2G17 protected when its inputs are driven while the power is off. This is needed for a data logging system that runs off batteries. I can send the PDF if my text is difficult to understand.

If the 74LVC2G17 cannot be used in this manner, Is the only option to use an Open Drain buffer that is always powered up with it's pull-up resistor connected to the SPI IC's switched power supply. This will increase the power since six buffers will be always powered on.

  • 0
    TI__Genius 14487 points

    Larry,

    I believe the SN74LVC2G17 buffer will work for your application. The datasheet states: "This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down." In the electrical characteristics section of the datasheet, the input and output pins will draw no more than 10 uA (Ioff) if 5.5 V is placed on them. Since your your system is 3.3 V, it should be even lower.

    James