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practical definition of monotonicity for logic clock inputs?

Tom McTaggart
Intellectual 345 points

When speciifying a clock input, what is a practial limit for when to consider a signal montonic or not? We typically judge it visually, "if it looks good, it is good". But for a given logic family (e.g. LVC, AHC), is there a reasonable way to at least estimate how much deviation (e.g. due to crosstalk) is accepatable?

  • 0
    TI__Genius 14487 points

    Tom,

    Good question. My guess is that so long as a transition is made within the maximum transition time specification, you should be fine. A way to calculate acceptable deviation could be the following:

    Acceptable deviation (ns) = Specified transition time (ns) - Nominal clock transition time (ns)

    In the meantime, I will ask my group to see if  they have any other input.

  • 0
    TI__Genius 14487 points

    Tom,

    I was just told that a clock signal is okay if the transition has a flat spot in it. However, if crosstalk or reflection in the line causes the edge to change direction at all, then that can cause errors in the operation of the part.