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Hello John
Unfortunately it does not come up in a known state. You could tie the clear low through a pull down resistor.
Hi,
In the SN74LV595A datasheet (http://www.ti.com/lit/gpn/sn74lv595a) on switching characteristic spec on page 9 - 11. There are 3 columns of spec. What are the differences between them ?
Under SN74LV595A, the minimum switching delay from SRCLK -> QH' is 1ns. If 2 devices are cascaded together, OH' of one connects to SER of another, will there be an issue ? SInce the hold time requirement for SER is 1.5ns (or 2ns for 5v supply).
CM.