IBIS model LSF0102

Sergio Pesenti

Other Parts Discussed in Thread: LSF0102, LSF0101

I am trying to run a transient simulation of the LSF0102 with HSPICE.

I downloaded the IBIS model from the webpage and set up a test bench instantiating the component as follows. I force the voltages of the two input pins 3 & 4 with pulse sources from 0 to 1.8V. I am expecting the two outputs 5 &6 to toggle between 0 and 3.3V. The reference voltages are set to 1.8V and 3.3V respectively. However, the outputs toggle between 200mV and 2.2V.

Either the model is wrong or my implementation is not appropriate?

.ibis dut
+ file ='lsf0102.ibs'
+ component ='LSF0102DCU'
+ mod_sel='LSF0101_IN=LSF0101_IN_33,LSF0101_IO=LSF0101_IO_33,LSF0101_IO_S=LSF0101_IO_33_S'
+ typ=typ

VGNDQ dut_1 0 dc=0
VRAQ dut_2 0 dc=1.8
VRBQ dut_7 0 dc=3.3
VENQ dut_8 0 dc=3.3
VA1Q dut_3 0 PULSE 0 1.8 5n 1n 1n 25n 50n
VA2Q dut_4 0 PULSE 0 1.8 5n 1n 1n 25n 50n
COUT1 dut_5 0 10p
COUT2 dut_6 0 10p
Rpu1 dut_3 dut_2 300
Rpu2 dut_4 dut_2 300
Rpu3 dut_5 dut_7 300
Rpu4 dut_6 dut_7 300

.TRAN 1f 100n

.end

over 10 years ago

0 Emrys Maier over 10 years ago

TI__Guru* 97066 points

I'm not very familiar with HSPICE, but from what I see here, you have 300 ohm pullups on each input/output, but no pullup from EN/VrefB to Vcc.

This app note goes over the specifics for using the LSF family of voltage translators: http://www.ti.com/lit/an/slva675b/slva675b.pdf

0 Sergio Pesenti over 10 years ago in reply to Emrys Maier

Prodigy 30 points

Hi Emrys,

Thanks for the application note. I found it very useful but it does not solve the problem. I reconfigured the test-bench with the 200kOhm but no current flows though it whereas I would expect it to allow the biasing of the switch gate. You may actually help in understanding why in HSPICE appears this internal node "dut_8_i" constantly equal to 0.5 (dut_8 beeing the enable pin). Is there someone else at TI who could help on the usage of this IBIS model?

.ibis dut
+ file ='lsf0102.ibs'
+ component ='LSF0102DCU'

VGND dut_1 0 dc=0.0

VREFA dut_2 0 dc=3.3
VREFB refb 0 dc=5.0

VA1Q dut_3 0 PULSE 0 3.3 5n 1n 1n 25n 50n
VA2Q dut_4 0 PULSE 0 3.3 15n 1n 1n 25n 50n

Cout5 dut_5 0 10p
Cout6 dut_6 0 10p
Rpu5 dut_5 refb 200
Rpu6 dut_6 refb 200

Rs dut_7 dut_8 0.0
Rref dut_8 refb 200e3

.TRAN 1f 100n

.end

0 Sergio Pesenti over 10 years ago in reply to Sergio Pesenti

Prodigy 30 points

I think I understood how the model works by reading these two documents, more specifically on the "series MOSFET" description:

http://www.eda.org/ibis/cookbook/cookbook-v4.pdf

http://www.vhdl.org/ibis/training/3com-docs/IBIS_Syntax.doc.

In brief, the connection between A and B pins is made using MOSFET table description. But the table assumes the gate voltage is fixed, equal to "Vcc", which is set by selecting the appropriate model. There is a table for each "Vds" value between A and B. The table provide current Ids versus Vgs, apparently calculated as Vcc-V(A) or Vcc-V(B) . Thus, to allow the MOSFET to turn off, such that the pull-up resistor brings the output voltage (B) high, we need the input (A) to go up to Vcc. However, the changes on the other pins like the enable are not considered in the model.

The following netlist works:

.option post

.ibis dut
+ file ='lsf0102.ibs'
+ component ='LSF0102DCU'
+ mod_sel='LSF0101_IN=LSF0101_IN_33,LSF0101_IO=LSF0101_IO_33,LSF0101_IO_S=LSF0101_IO_33_S'
*+ typ=typ

VGND dut_1 0 dc=0.0
VREFA refa 0 dc=3.3
VREFB refb 0 dc=5.0

VA1Q dut_3 0 PULSE 0 3.3 5n 1n 1n 25n 50n
VA2Q dut_4 0 PULSE 0 3.3 15n 1n 1n 25n 50n

C5 dut_5 0 5p

C6 dut_6 0 5p
R5 dut_5 refb 240
R6 dut_6 refb 240

Ren dut_7 dut_8 0

Rrefb dut_8 refb 0
Rrefa dut_2 refa 0

.TRAN 1f 100n
.end

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IBIS model LSF0102